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preliminary rev. 0.11 5/08 copyright ? 2008 by silicon laboratories si823x this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si823x 0.5 and 4.0 a iso drivers features applications description the si823x isolated driver family combines two independent, isolated drivers into a single package. th e si8230/1/3/4 are high-side/low-side drivers, and the si8232/5 are dual low-side drivers. versions with peak output currents of 0.5 a (si8230/1/2) and 4.0 a (si8233/4/5) are available. all drivers operate with a maximum supply voltage of 24 v. these drivers utilize silicon labs' prop rietary silicon isolation technology, which provides 600 v dc (2.5 kv acrms ) withstand voltage per ul1577, and fast 50 ns propagation times. driver outputs can be grounded to the same or separate grounds or connected to a positive or negative voltage. the ttl level compatible inputs are available in individual control input (si8230/2/3/5) or pwm input (si8231/4) configurations. high integration, low propagation delay, small installed size, flexibility, and cost-effectiveness make the si823x family ideal for a wide range of isolated mosfet/igbt gate drive applications. block diagrams two completely isolated drivers in one package 2.5 kv rms output-to-input differential voltage 600 vdc peak driver-to-driver differential voltage hs/ls and dual ls versions up to 8 mhz switching frequency 0.5 a peak output (si8230/1/2), 4.0 a peak output (si8233/4/5) independent hs and ls inputs or pwm input versions common-mode transient immunity >35 kv/s overlap protection and programmable dead time (si8230/1/3/4) operating temperature range ?40 to +125 c ul/vde/csa approval (pending) power delivery systems motor control systems lighting control systems plasma displays gndi vib vddi via vdda voa gnda vob vddb gndb disable dt uvlo 2.5kv isolation 2.5kv isolation gndi vddi pwm vdda voa gnda vob vddb gndb disable dt uvlo 2.5kv isolation 2.5kv isolation gndi vddi via vdda voa gnda vob vddb gndb disable uvlo 2.5kv isolation 2.5kv isolation vib overlap protection, programmable dead time, control gating programmable dead time, control gating control gating si8230/3 si8231/4 si8232/5 patents pending pin assignments via vib vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8230 si8233 pwm nc vddi gndi disable dt nc vddi vdda voa gnda nc nc vddb vob gndb si8231 si8234 via vib vddi gndi disable nc nc vddi vdda voa gnda nc nc vddb vob gndb si8232 si8235
si823x 2 preliminary rev. 0.11
si823x preliminary rev. 0.11 3 t able of c ontents section page 1. top-level block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1. test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 5. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5.1. products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2. device behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5.3. power supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4. power dissipation considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.5. layout considerat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.7. programmable dead time and overlap protection . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1. high-side/low-side driv er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2. dual low-side driv er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8. package outline: wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
si823x 4 preliminary rev. 0.11 1. top-level block diagrams figure 1. si8230/3 two-input high-side/low-side isolated drivers figure 2. si8231/4 single-input high-side/low-side isolated drivers si8230/3 uvlo uvlo gndi vib vddi via vdda voa gnda vob vddi vddi isolation vddi vddb gndb disable isolation uvlo dt control & overlap protection dt si8231/4 uvlo uvlo gndi vddi pwm vdda voa gnda vob vddi vddi isolation vddi vddb gndb disable isolation uvlo dt control & overlap protection dt lpwm lpwm
si823x preliminary rev. 0.11 5 figure 3. si8232/5 dual low-side isolated drivers si8232/5 uvlo vdda voa gnda vob vddi isolation vddi vddb gndb uvlo via isolation uvlo gndi vib vddi vddi disable
si823x 6 preliminary rev. 0.11 2. pin descriptions table 1. si8230/3 two-input hs/ls isolated driver pin name description 1 via non-inverting logic in put terminal for driver a. 2 vib non-inverting logic in put terminal for driver b. 3 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 4 gndi input-side ground terminal 5 disable device disable. when high, th is input uncondit ionally drives outputs voa, vob low. it is strongly recommended that this input be connect ed to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 dt dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. defaults to 7 ns dead time when con- nected to vddi or left open (see "5.7.progr ammable dead time and overlap protection" on page 16). 7 nc no connection. 8 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 9 gndb ground terminal for driver b. 10 vob driver b output (low-side driver). 11 vddb driver b power supply voltage terminal; connect to a source of 10 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver a output (high-side driver). 16 vdda driver a power supply voltage terminal; connect to a source of 10 to 24 v. table 2. si8231/4 pwm input hs/ls isolated driver pin name description 1 pwm pwm input 2 nc no connection. 3 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 4 gndi input-side ground terminal. 5 disable device disable. when high, this input uncond itionally drives outputs voa, vob low. it is strongly recommended that this input be connect ed to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 dt dead time programming input. the value of the resistor connected from dt to ground sets the dead time between output transitions of voa and vob. defaults to 7 ns dead time when con- nected to vddi or left open (see "5.7.progr ammable dead time and overlap protection" on page 16). 7 nc no connection.
si823x preliminary rev. 0.11 7 8 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 9 gndb ground terminal for vob driver output. 10 vob driver b output (low-side driver). 11 vddb driver b power supply voltage terminal; connect to a source of 10 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver a output (high-side driver). 16 vdda driver a power supply voltage terminal; connect to a source of 10 to 24 v. table 3. si8232/5 dual ls isolated driver pin name description 1 via non-inverting logic in put terminal for driver a. 2 vib non-inverting logic in put terminal for driver b. 3 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 4 gndi input-side ground terminal. 5 disable device disable. when high, this input unconditiona lly drives outputs voa, vob low. it is strongly recommended that this input be connect ed to external logic level to avoid erroneous operation due to capacitive noise coupling. 6 nc no connection. 7 nc no connection. 8 vddi input-side power supply terminal; connect to a source of 4.5 to 5.5 v. 9 gndb ground terminal for vob driver output. 10 vob driver b output. 11 vddb driver output vob power supply voltage terminal; connect to a source of 10 to 24 v. 12 nc no connection. 13 nc no connection. 14 gnda ground terminal for driver a. 15 voa driver b output. 16 vdda driver a power supply voltage terminal; connect to a source of 10 to 24 v. table 2. si8231/4 pwm input hs/ls isolated driver (continued)
si823x 8 preliminary rev. 0.11 3. electrical specifications table 4. electrical characteristics 4.5 v < vddi< 5.5 v, vdda = vddb = 12 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test conditions min typ max units dc specifications input-side power supply voltage vddi 4.5 ? 5.5 v driver supply voltage vdda, vddb voltage between vdda and gnda, and vddb and gndb 10 ? 24 v input supply quiescent current iddi(q) ? ? 11 ma output supply quiescent current idda(q), iddb(q) current per channel ? ? 3.0 ma input supply active current iddi pwm freq = 500 khz ? 11 ? ma input pin leakage current iia, iib, ipwm, idisable ?10 ? +10 a dc logic high input threshold vih 2.0 ? ? v logic low input threshold vil ? ? 0.8 v logic high output voltage voah, vobh ioa, iob = ?1 ma vdda ? 0.04 ?? v logic low output voltage voal, vobl ioa, iob = 1 ma ? ? 0.04 v output short-circuit pulsed sink current ioa(scl), iob(scl) si8230/1/2, figure 4 ? 0.5 ? a si8233/4/5, figure 4 ? 4.0 ? output short-circuit pulsed source current ioa(sch), iob(sch) si8230/1/2, figure 5 ? 0.25 ? si8233/4/5, figure 5 ? 2.0 ? output sink resistance r on(sink) si8230/1/2 ? 5.0 ? si8233/4/5 ? 1.0 ? output source resistance r on(source) si8230/1/2 ? 15 ? si8233/4/5 ? 2.7 ? vddi undervoltage threshold vddiuv+ vddi rising 3.60 ? 4.40 v vddi negative-going lockout hysteresis vddih? vddi falling ? 300 ? mv *note: t dd is the minimum overlap time without trigge ring overlap protection (si8230/1/3/4 only).
si823x preliminary rev. 0.11 9 vdda, vddb positive-going undervoltage threshold vddauv+, vddbuv+ vdda, vddb rising 7.5 8.5 9.5 v vdda, vddb negative-going undervoltage threshold vddauvh?, vddbuvh? vdda, vddb falling 7.0 8.0 9.0 v ac specifications propagation delay t phl , t plh cl = 200 pf ? ? 50 ns minimum overlap time tdd dt = vddi, note* ? ?0.4 ? ns programmed dead time dt fig 2.3, rdt = 100 k ? 1,000 ? ns fig 2.3, rdt = 6 k ? 72 ? output rise and fall time t r ,t f c l = 200 pf (si8230/1/2) ? ? 12 ns c l = 200 pf (si8233/4/5) ? ? 20 shutdown time from disable true tsd ??50ns restart time from disable false trestart ? ? 50 ns device start-up time tstart time from vdd_ = vdd_uv+ to voa, vob = via, vib ??2 s table 4. electrical characteristics (continued) 4.5 v < vddi< 5.5 v, vdda = vddb = 12 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test conditions min typ max units *note: t dd is the minimum overlap time without trigge ring overlap protection (si8230/1/3/4 only).
si823x 10 preliminary rev. 0.11 3.1. test circuits figures 4 and 5 depict sink current and source current test circuits. figure 4. sink current test circuit figure 5. source current test circuit input 1 f 100 f 10 rsns 0.1 si823x 1 f cer 10 f el vdda = vddb = 12 v in_ out_ vss vdd schottky 50 ns 200 ns measure input waveform gnd vddi vddi (5 v) 5 v + _ input 1 f 100 f 10 rsns 0.1 si823x 1 f cer 10 f el vdda = vddb = 12 v in_ out_ vss vdd 50 ns 200 ns measure input waveform gnd vddi schottky vddi (5 v) 5 v + _
si823x preliminary rev. 0.11 11 table 5. absolute maximum ratings parameter symbol min typ max units storage temperature t stg ?65 +150 c ambient temperature under bias t a ?40 +125 c input-side supply voltage v ddi ?0.6 6.0 v driver-side supply voltage v ia , v ib ?0.6 24 v voltage on any pin with respect to ground (not including iin, iout) v in ?0.5 vdd + 0.5 v lead solder temperature (10 sec.) ? ? ? 260 degrees c dc isolation (output to output) ? ? ? 1,000 vdc dc isolation (input to output) ? ? ? 3,000 vdc note: permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. regulatory information ul the si823x is certified under ul1577 component recognition program to provide basic insulation to 2500 v rms (1 minute). it is production tested > 3000 v rms for 1 second. for more details, see file e257455. table 7. insulation and safety-related specifications parameter symbol test condition value unit minimum air gap (clearance) l(io1) 7.7 min mm minimum external tracking (creepage) l(io2) 8.1 mm minimum internal gap (internal clearance) 0.008 min mm resistance (input-output) 1 r io 10 12 capacitance (input-output) 1 c io f=1mhz 1.4 pf input capacitance 2 c i 4.0 pf notes: 1. to determine resistance and capacitance, the si823x is converted into a 2-terminal dev ice. pins 1?8 are shorted together to form the first terminal and pins 9?16 are shorted together to form the second terminal. the parameters are then measured between these two terminals. 2. measured from input pin to ground.
si823x 12 preliminary rev. 0.11 4. overview the si823x isodrivers are dual output drivers for isol ated high-side/low-side and dual low-side gate drive applications. these products utilize silicon lab oratories' proprietary silicon isolator techno logy, which enables fast propagation time while withstanding 600 v dc from the in put to either output and between outputs. the operation of this isolator is analogous to that of an optocoupler, ex cept that an rf carrier is modulated instead of light. this simple architecture provides a robust, isolated data path and requires no spec ial considerations or initialization at start-up. as shown in figure 6, an isolation channel consists of an rf transmitter and receiver separated by an rf transformer. figure 6. isolator operation input "a" turns the rf carrier on when high and off when low. the carrier is transmitted through the rf transformer to the output side demodulator, which consists of a receiver tuned to the carrier frequency. the demodulator asserts output "b" when sufficient in-band energy is detected. the driver output stage follows that of output b. transmitter receiver rf oscillator modulator demodulator a b rf transformer
si823x preliminary rev. 0.11 13 5. application information the si823x family of isolated driver s consists of high-side, low-side, and dual low-side driver configurations. 5.1. products table 8 shows the configuration and functional overview for each product in this family. 5.2. device behavior table 9 contains truth tabl es for the si8230/ 3, si8231/4, and si8232/5 families. table 8. si823x family overview part number configuration overlap protection programmable dead time inputs peak output current (a) si8230 high-side/low side via, vib 0.5 si8231 high-side/low side pwm 0.5 si8232 dual low side ? ? via, vib 0.5 si8233 high-side/low side via, vib 4.0 si8234 high-side/low side pwm 4.0 si8235 dual low side ? ? via, vib 4.0 table 9. si823x family truth table si8230/3 (high-side/low-side) truth table via, vib inputs vddi state disable voa/vob output notes h powered l h output transition occurs af ter internal dead time expires. l powered l l output transition occurs after internal dead time expires. x unpowered x l output returns to input state within 500 ns of vddi power restoration. x powered h l device is disabled. si8231/4 (pwm input high-side/low-side) truth table pwm input vddi state disable voa/vob output notes h powered l h output transition occurs after internal dead time expires. l powered l l output transition occurs after internal dead time expires. x unpowered x l output returns to input state within 500 ns of vddi power restoration. x powered h l device is disabled. si8232/5 (dual low-side) truth table via, vib inputs vddi state disable voa/vob output notes h powered l h output transition occurs immediately (no internal dead time). l powered l l x unpowered x l output returns to input state within 500 ns of vddi power restoration. x powered h l device is disabled.
si823x 14 preliminary rev. 0.11 5.3. power supply connections isolation requirements mandate individual supplies fo r vddi, vdda, and vddb. the decoupling caps for these supplies must be placed as close to the vdd pins of the si823x as possible. the optimum values for these capacitors depend on load current and the distance be tween the chip and the regulator that powers it. low effective series resistance (esr) capacitors, such as tantalum, are recommended. 5.4. power dissipation considerations proper system design must assure that the si823x operates within safe therma l limits across the entire load range. the si823x total power dissipation is the sum of the powe r dissipated by bias supply current, internal switching losses, and power delivered to the load. equation 1 show s total si823x power dissipation. in a non-overlapping system, such as a high-side/low-side driver, n = 1. for a dual low-side driver with each driver having an independent load, n can have a maximum value of 2, corresponding to a 100% overlap between the two outputs. equation 1. the maximum power dissipation allowable for the si823x is a function of the package thermal resistance, ambient temperature, and maximum allowable juncti on temperature, as shown in equation 2: equation 2. substituting values for pdmax tjmax, ta, and ja into equation 2 results in a maximum allowable total power dissipation of 1.1 w. maximum allowable load is found by substituting this limit and the appropriate datasheet values from table 4 on page 8 into equation 1 and si mplifying. the result is equation 3 (0.5 a driver) and equation 4 (4.0 a driver), both of which assume vddi = 5 v and vdda = vddb = 18 v. equation 3. equation 4. p d v ddi i ddi 2v ddo i qout c int v ddo 2 f + () 2n c l v ddo 2 f () ++ where: p d is the total si823x device power dissipation (w) i ddi is the input-side maximum bias current (3 ma) i qout is the driver die maximum bias current (5 ma) c int is the internal parasitic capacitance (75 pf for the 0.5 a driver and 370 pf for the 4.0 a driver) v ddi is the input-side vdd supply voltage (4.5 to 5.5 v) v ddo is the driver-side supply voltage (10 to 24 v) f is the switching frequency (hz) n is the overlap constant (max value = 2) = p dmax t jmax t a ? ja --------------------------- where: p dmax = maximum si823x power dissipation (w) t jmax = si823x maximum junction temperature (145 c) t a = ambient temperature (c) ja = si823x junction-to-air thermal resistance (105 c/w) f = si823x switching frequency (hz) c l(max) 1.4 10 3 ? f -------------------------- 7.5 ? 10 11 ? = c l(max) 1.4 10 3 ? f -------------------------- 3.7 ? 10 10 ? =
si823x preliminary rev. 0.11 15 equation 1 and equation 2 are graphed in figure 7 where the points along the load line represent the package dissipation-limited value of cl for the corresponding switching frequency. figure 7. max load vs. switching frequency 5.5. layout considerations it is most important to minimize ringing in the drive path and noise on the si823x vdd lines. care must be taken to minimize parasitic inductance in these pa ths by locating the si823x as close to the device it is driving as possible. in addition, the vdd supply and ground trace paths must be kept short. for this re ason, the use of power and ground planes is highly recommended. a split ground plane system having separate ground and vdd planes for power devices and small signal components provides the best overall noise performance. 5.6. device operation device behavior during start-up, normal operation and shutdown is shown in figure 8, where uvlo+ and uvlo- are the positive-going and negative-going thresholds respectively. note that outputs voa and vob default low when input side power su pply (vddi) is not present. 5.6.1. device startup outputs voa and vob are held low during power-up un til vdd is above the uvlo threshold for time period tstartup. following this, the outputs fo llow the states of inputs via and vib. 5.6.2. under voltage lockout (uvlo) uvlo is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. the input (control) side, driver a and driver b, each have their own under voltage lockout monitors. the si823x input side enters uvlo when vddi < v iuvh? , and exits uvlo when vddi > vdd iuv+ . the driver outputs, voa and vob, remain low when the input side of the si823x is in uvlo and their respective vdd supply (vdda, vddb) is within toler ance. each driver output can enter or ex it uvlo independently. for example, voa unconditionally enters uvlo when vdda falls below vdd auv? and exits uvlo when vdda rises above vdd auv+ . 10 100 1,000 10,000 0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 frequency (khz) load (pf) 0.5 a 4 a
si823x 16 preliminary rev. 0.11 figure 8. device behavior during normal operation and shutdown 5.6.3. control inputs via, vib, and pwm inputs are high-true, ttl level-compatible logic inputs. a logic high signal on via or vib causes the corresponding output to go high. for pwm inpu t versions (si8231/4), voa is high and vob is low when the pwm input is high, and voa is low and vob is high when the pwm input is low. 5.6.4. disable input when brought high, the disable input un conditionally drives voa and vob lo w regardless of th e states of via and vib. device operation term inates within tsd after disable = v ih and resumes within trestart after disable = v il . the disable input has no effect if vddi is be low its uvlo level (i.e. voa, vob remain low). 5.7. programmable dead time and overlap protection all high-side/low-side drivers (si823 0/1/3/4) include programmable overlap protection to prevent outputs voa and vob from being high at the same time . these devices also include programm able dead time, which adds a user- programmable delay between transitions of voa and vob (f igure 2.3a). when enabled, dead time is present on all transitions, even after overlap recovery (figure 2.3b). the amount of dead time delay (dt) is programmed by a single resistor (rdt) connected from the dt input to ground per equation 5. equation 5. via voa disable vddi uvlo- vdda tstart tstart tstart tsd trestart tphl tplh uvlo+ uvlo- uvlo+ tsd dt 11 rdt where: dt dead time (ns) and rdt dead time programming resistor (k ) = =
si823x preliminary rev. 0.11 17 the device driving via and vib should provide a minimum dead time of tdd to avoid activating overlap protection. input/output timing waveforms for the two-input drivers are shown in figure 8, and dead time waveforms are shown in figure 9. if dead time programming is not used, it is strongly recommended that dt be connected to vddi to avoid capacitive noise coupling; however, dt may also be left unconnected. note: if dt is left floating, there can be no dc leakage path between ground and dt. avoid adding parasitic or component capacitance in parallel with rdt. figure 8. input/output waveforms for high side/low side two-input drivers figure 9. dead time waveforms for high side/low side two-input drivers via vib voa vob ` a b c d e f g h i ref description a normal operation: via high, vib low. b normal operation: vib high, via low. c contention: via = vib = high. d recovery from contenti on: via transitions low. e normal operation: via = vib = low. f normal operation: via high, vib low. g contention: via = vib = high. h recovery from contenti on: vib transitions low. i normal operation: vib transitions high. via vib voa vob dt dt 10% 10% 90% 90% 50% vob a. typical dead time operation via voa vob dt dt vib dt dt overlap overlap b. dead time operation during overlap
si823x 18 preliminary rev. 0.11 6. applications the following examples illustrate typical circuit configurations using the si823x. 6.1. high-side/low-side driver figure 10a shows the si8230/3 controlled using the via an d vib input signals, and figure 10b shows the si8231/4 controlled by a single pwm signal. figure 10. si823x in half-bridge application for both cases, d1 and cb form a conventional bootstrap circuit that allows voa to operate as a high-side driver for q1, which has a maximum drain voltage of 600 v. vob is connected as a conventi onal low-side driver. note that the input side of the si823x requires vdd in the r ange of 4.5 to 5.5 v, while th e vdda and vddb output side supplies must be between 10 and 24 v. also note that th e bypass capacitors on the si823x should be located as close to the chip as possible. moreover, it is recommen ded that 0.1, 1, and 10 f bypass capacitors be used to minimize high frequency and maximize performance. si8230/3 cb 600v max gndi vddi via vdda voa gnda vob vddi vddb gndb disable vdd2 dt rdt controller vib c1 1uf out1 out2 i/o q1 q2 d1 vddb c3 10uf c2 1 f si8231/4 cb 600v max gndi vddi pwm vdda voa gnda vob vddi vddb gndb disable dt rdt controller c1 1uf pwmout i/o q1 q2 d1 vddb c3 10uf ab vdd2 c2 1 f
si823x preliminary rev. 0.11 19 6.2. dual low-side driver figure 11 shows the si823x configured as a dual low-side dr iver. note that the drain voltages of q1 and q2 can be referenced to a common ground or to different grounds with as much as 600 v dc between them. figure 11. si8235 in a dual low-side driver application si8235 gndi vddi via vdda voa gnda vob vddi vddb gndb disable controller vib ph1 ph2 i/o q1 q2 vdda vddb c3 10 f c2 10 f c1 10 f
si823x 20 preliminary rev. 0.11 7. ordering guide part number inputs configuration peak output current (a) package temp range ( c) SI8230-A-IS via, vib high side/low side 0.5 16so wide ?40 to +125 si8231-a-is pwm high side/low side si8232-a-is via, vib dual low side si8233-b-is via, vib high side/low side 4.0 si8234-b-is pwm high side/low side si8235-b-is via, vib dual low side
si823x preliminary rev. 0.11 21 8. package outline: wide body soic figure 12 illustrates the package details for the quad -channel digital isolator. tabl e 10 lists the values for the dimensions shown in the illustration. all packages are pb-free and rohs comp liant. moisture sensitivity level is msl3 with peak reflow temperature of 260 c according to the jedec industry classification and peak solder temperature. figure 12. 16-pin wide body soic table 10. package diagram dimensions symbol millimeters min max a ? 2.65 a1 0.1 0.3 d 10.3 bsc e 10.3 bsc e1 7.5 bsc b 0.31 0.51 c 0.20 0.33 e 1.27 bsc h 0.25 0.75 l 0.4 1.27 0 7
si823x 22 preliminary rev. 0.11 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: powerproducts@silabs.com internet: www.silabs.com/power silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. the sale of this product contains no licens es to power-one?s intellectual property. contact power-one, inc. for appropriate lic enses.

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